Nov 08, 2023

Flip Flops

Simplified Verilog implementation for positive-edge D flip-flops.

Verilog Code

module flipFlop(
    input d, clk, reset,
    output reg q
);
    always @(posedge clk) begin
        if (!reset) q = 0;
        else q = d;
    end
endmodule

Waveform

Untitled

Schematic

Untitled